1. Field of the Invention
The present invention generally relates to electrically erasable non-volatile semiconductor memory devices (EEPROMs), and more particularly to a so-called flash memory that stores information in the form of electric charges accumulated in a floating gate.
2. Description of the Related Art
Recently, intensive efforts are being made on research and development of so-called flash memories. Flash memories, having a compact and solid construction, are expected to replace bulky and fragile conventional hard disk devices in various computers, including laptops. As each memory cell in the flash memory is formed of a single transistor similar to the memory cell transistor of conventional dynamic random access memories, flash memories can easily realize high integration density and large storage capacity. Further, flash memories have no movable parts such as driving motors, and consume little electric power.
In flash memories, each memory cell has a construction similar to a MOS transistor and includes a source region and a drain region formed in a semiconductor substrate. Further, there is provided a floating gate between the substrate and a control electrode such that the floating gate is insulated by a thin tunneling insulation film, wherein the control electrode corresponds to the gate electrode of conventional MOS transistors. When storing information, a predetermined control voltage is applied to the gate electrode. Thus, carriers flowing from the source region to the drain region are accelerated in the vicinity of the drain region and are injected into the floating gate through the aforementioned tunneling insulation film. The carriers, and hence the electric charges thus injected to the floating gate, are held therein stably and urge the potential level of the floating gate to a predetermined level. As a result, the flow of carriers from the source to the drain is controlled to on and off states by the carriers stored in the floating gate. In other words, it is possible to read the electric charges, and hence the information stored in the floating gate, by detecting the drain current of the memory cell transistor. When erasing information thus stored, a potential is applied to the control electrode such that the electric charges in the floating gate are expelled, simultaneously, to a potential that is applied to the semiconductor substrate or to the source region in the substrate for extracting the electric charges from the floating gate. As a result, the electric charges in the floating gate are dissipated, through the aforementioned tunneling insulation film, either to the semiconductor substrate or to the source region in the substrate.
FIG. 1 schematically shows the construction of the memory cell in the conventional flash memory described above.
Referring to FIG. 1, the memory cells are formed on a semiconductor substrate 10, which may be doped to the p-type for example, in an arrangement of rows and columns, wherein each of the memory cells includes an n.sup.+ -type source region 11a and an n.sup.+ -type drain region 11b on the substrate 10, spaced such that the regions 11a and 11b are separated from each other by a p-type channel region 10a interposed therebetween. The part of the semiconductor substrate 10 corresponding to the channel region 10a is covered by a tunneling insulation film 12a, and a floating gate electrode 12 is provided on the tunneling insulation film 12a. Further, the gate electrode 12 is covered by an interlayer insulation film 13a, and a control electrode 13 is provided on the interlayer insulation film 13a.
When storing information, a negative source voltage Vs is applied to the source region 11a, and a positive drain voltage Vd is applied to the drain region 11b, such that electrons flow from the source region 11a to the drain region 11b through the channel region 10a. Further, a positive control voltage Vg is applied to the control electrode 13. Thereby, the electrons flowing from the source region 11a to the drain region 11b are accelerated in the channel region 10a and acquire a large kinetic energy in the vicinity of the drain electrode 11b. The electrons accelerated are injected into the floating gate 12 after transit through the tunneling insulation film in the form of Fowler-Nordheim tunneling current that is caused to flow as a result of the positive voltage of the control electrode 13. The electrons thus injected into the floating gate 12 are held stably therein with little leakage, even when the power is shut off. When negative electric charges are thus accumulated in the floating gate 12, the MOS transistor, formed between the source region 11a and the drain region 11b, no longer turns on due to the negative charges of the floating gate 12, even when a control voltage Vg is applied to the control electrode 13 so as to cause a turning-on of the MOS transistor. Thus, by detecting the drain voltage Vd, it becomes possible to read the information stored in the memory cell.
When updating or erasing information stored in a memory cell, the control voltage Vg applied to the control electrode 13 is set to a large negative voltage. Simultaneously, a positive voltage is applied to the substrate 10 as a substrate voltage. Alternatively, a positive voltage is applied to the source region 11a as the source voltage Vs. As a result, the electrons accumulated in the floating gate 12 are expelled, respectively and alternatively, either to the substrate 10 or to the source region 11a provided in the substrate 10. As a result, the information stored in the memory cell is erased.
FIG. 2(A) shows the operation of a flash memory cell of the so-called channel erase type wherein the electrons in the floating gate 12 are dissipated to the substrate 10 when erasing information. Further, FIG. 2(B) shows the setting of the source voltage Vs, the drain voltage Vd, the control voltage Vg and the substrate voltage V.sub.SUB for each of the writing, reading and erasing modes for the memory cell of FIG. 2(A). In the drawing, the tunneling insulation film 12a and the interlayer insulation film 13a are omitted for the sake of simplicity.
Referring to FIG. 2(B), a large negative voltage V.sub.MM is applied to the control electrode 13 in the erase mode. Simultaneously, a positive supply voltage Vcc is applied to the substrate 10. As a result, the electrons in the floating gate 12 are dissipated to the substrate 10 along a path (1) shown schematically in FIG. 2(A). In this process, the source region Vs and the drain region Vd assume an opened or floating state. When in the write mode, on the other hand, the control voltage Vg applied to the control electrode 13 is set to a large positive voltage V.sub.PP. Simultaneously, the source region 11b is grounded (Vs=0 V) and the positive supply voltage Vcc is applied to the drain region 11b. As a result, the electrons are caused to flow from the source region 11a to the drain region 11b, and accelerated electrons are injected to the floating gate 12 in the form of tunneling current, after passing through a path (2) schematically shown in FIG. 2(A). In the read mode, on the other hand, the supply voltage Vcc is applied to the control electrode 13 via a selected word line, and the drain voltage Vd is set to a positive voltage of about 1 V. Further, the source region 11a and the substrate 10 are grounded (Vs=0 V). As a result, the electrons flow from the source region 11a to the drain region 11b in the case where there is no electron accumulation in the floating gate 12 and the transistor of FIG. 2(A) is turned on. When the electrons are accumulated in the floating gate 12, on the other hand, the flow of electrons through the channel region 10a does not occur due to the electric charges of the electrons. In other words, the transistor of FIG. 2(A) does not turn on. Thus, by detecting the change of the drain voltage Vd, caused as a result of the turning-on and turning-off of the foregoing transistor by means of a sense amplifier, it becomes possible to read the information stored in the floating gate 12.
FIGS. 3(A) and 3(B) show the construction and operation of a flash memory cell that causes a dissipation of the electric charges of the floating gate 12 to the source region 11a, and not to the substrate 10, when erasing information. Similarly to FIG. 2(A), the tunneling insulation film 12 and the interlayer insulation film 13a are omitted in FIG. 3(A). Since the write mode operation and the read mode operation of the memory cell of FIGS. 3(A) and 3(B) are identical with those of the memory cell of FIGS. 2(A) and 2(B), only the erase mode operation will be described below.
Referring to FIG. 3(B), the source voltage Vs applied to the source region 11a is set to the positive supply voltage Vcc in the erase mode. Further, the control voltage Vg applied to the control electrode 13 is set to the negative high voltage V.sub.MM. On the other hand, the substrate voltage V.sub.SUB is set to 0 V. Further, the drain region 11b is set to an opened state. As a result, the electrons in the floating gate 12 are dissipated to the source region 11a along the path (1) shown schematically in FIG. 3(A).
In both the device of FIGS. 2(A) and 2(B) and the device of FIGS. 3(A) and 3(B), unwanted erase of memory cells is avoided by applying the positive supply voltage Vcc to the memory cell not to be erased, as the control voltage Vg.
FIG. 4 shows an example of a flash memory that uses the memory cell of FIG. 2(A). Referring to FIG. 4, the flash memory includes an n-type well 10A formed in the p-type substrate 10, wherein another, p-type well 10B is formed within the n-type well 10A. In the p-type well 10B, n.sup.+ -type diffusion regions are formed in correspondence to the source region 11a and the drain region 11b of FIG. 2(A), and a number of floating electrodes 12 as well as control electrodes 13 are arranged in rows and columns. By forming a plurality of memory cells in the well 10B and applying an erase voltage V.sub.PW to the well 10B, it becomes possible to achieve simultaneous erase of information in each of the cells. As such a double well structure, which includes the n-type well 10A and the p-type well 10B, forms a parasitic pnp transistor when constructed on a p-type substrate such as the substrate 10 of FIG. 4, it is necessary to apply a voltage V.sub.NW to the n-type well 10A when applying the erase voltage V.sub.PW to the well 10B, in order to avoid the conduction of the transistor.
FIG. 5 shows the circuit construction of the flash memory shown in FIG. 4.
Referring to FIG. 5, memory cells C, each having the construction of FIG. 2(A), are disposed in rows and columns on the well 10B which in turn is formed on the semiconductor substrate 10 as shown in FIG. 4; those memory cells C aligned in the row direction have respective control electrodes 13 connected commonly with each other by a word line WL as shown in FIG. 5. On the other hand, those memory cells aligned in the column direction have respective drain regions 11b connected commonly with each other by a bit line BL. The word line WL is selected, via an address buffer 23 and a row decoder 24, in response to the row address data supplied to the flash memory device, and the control voltage Vg shown in FIG. 2(B) is applied to the selected word line WL. Particularly, the row decoder 24 supplies, in the erase mode, the negative erase voltage V.sub.MM shown in FIG. 2(B) exclusively to the selected word line WL, based upon the supply voltage supplied from a decoder power supply circuit 25. The row decoder 24 further supplies the normal, positive supply voltage Vcc to the unselected word line WL in order to avoid unwanted erase. As a result, only those memory cells C that are connected to the selected word line (i.e., a memory cell block) are erased simultaneously. In other words, the memory cells of the selected memory cell block are erased simultaneously.
In the construction of FIG. 5, it will be noted that each bit line BL is provided with a corresponding column selection transistor T, wherein the column selection transistor T is selectively turned on and turned off via a column address buffer 21 and a column decoder 22, based upon column address data supplied to the column decoder 22. Each bit line BL is connected to a common data line DL via a corresponding column selection transistor T, and an ordinary sense amplifier 27 connected to the line DL discriminates the logic value of the information read out from the selected memory cell C that has been selected in response to the supplied address data. The output of the sense amplifier 27 is supplied via an input/output buffer 28 to an output terminal. Further, there is provided a write amplifier 26 in connection to the line DL for supplying an information signal, which has been supplied via the input/output buffer 28, to a selected bit line BL via the switch transistor T. Further, the circuit of FIG. 5 includes an erase power supply circuit 29 for applying the erase voltages V.sub.NW and V.sub.PW to the wells 10A and 10B of FIG. 4 in the erase mode, in addition to the foregoing circuits.
FIG. 6 shows a block diagram of a flash memory that uses the memory cell of FIGS. 3(A) and 3(B). As the flash memory of FIG. 6 has a construction generally identical to the device of FIG. 5, those parts of FIG. 6 corresponding to FIG. 5 are designated by the same reference numerals and the description thereof will be omitted.
In the flash memory having a construction of FIG. 6, the source regions of each memory cell transistor C are connected commonly to an erase power supply circuit 29', while the erase power supply circuit 29' produces a source voltage Vs as indicated in FIG. 3(B). In correspondence to this, the decoder circuit 25 supplies the erase voltage V.sub.MM to the selected word line WL and the positive supply voltage Vcc to the unselected word line WL.
Flash memories of the type that erase information by causing a dissipation of electric charges to the substrate have the problem of the wells 10A and 10B forming a parasitic bipolar transistor with the substrate 10, as already explained. Thus, in order to avoid turning-on of the parasitic bipolar transistor, it is necessary to apply a suitable biasing to the substrate 10 as well as to the wells 10A and 10B. Conventionally, the bias voltage V.sub.NW applied to the well 10A and the bias voltage V.sub.PW applied to the well 10B, have been set equal to the positive supply voltage Vcc. On the other hand, the existence of parasitic resistances 10A and 10B in the p-type well 10A and in the n-type well 10B raises a problem that there may occur a transient state wherein the parasitic bipolar transistor turns on. When such a turning-on of the parasitic bipolar transistor occurs, the operation of the flash memory becomes unstable.
It should be noted that the construction to apply the so-called anti-disturb voltage, with the magnitude of about Vcc, to unselected word lines to avoid unwanted erasing of information in unselected memory cell blocks, is employed not only in the flash memories of the type which cause the dissipation of electric charges to the substrate in the erase mode but also in the flash memories of the type in which the electric charges are dissipated to the source region. On the other hand, such a construction has a problem that there may occur a transient state wherein the anti-disturb voltage is not effectively applied. In such a case, there is a risk which the information that should be retained is unwantedly erased from the memory cell.
Further, the flash memories of the type shown in FIG. 4, that dissipate electric charges in the floating gate 12 to the well 10B in the erase mode, tend to have a problem that the p-n junction, formed between the well 10B and the n-type diffusion region 11a that forms the drain region or source region, is subjected to a forward biasing in the erase mode. When this occurs, the bit line BL as well as the source region are charged to the level of the supply voltage Vcc. Further, in the flash memories having the construction to dissipate electric charges in the floating gate to the source region 11a in the erase mode as shown in FIG. 3(A), there arises a problem in that the drain region 11b assumes an opened state in the erase mode. Further, the anti-disturb voltage is applied to the unselected word lines in this state. Thus, while it is possible to dissipate the positive electric charges of the Vcc level on the bit line BL by turning the memory cell transistor on, there occurs a problem in that the electrons are accelerated in the channel region 11 a during the dissipation process, as they travel from the source region 11a to the drain region 11b (see FIG. 3A), and are injected into the floating gate 12 in the form of a tunneling current. In other words, there may occur an unwanted writing of information into the floating gate while conducting a discharging of the bit line BL in the construction of FIG. 3(A).